MIPS 32-bit Processor Design
Description:
Designed and implemented a 32 bit dual-core cached pipeline processor on an FPGA. Learnt and implemented a Pipelined design along with branch prediction, set associative caching and cache-coherence using the MSI protocol.
My brief intro to computer architecture
I wrote a brief quora answer that introduces computer architecture by starting bottom up on how an IF condition is implemented in hardware and how that hardware has evolved into the computers we have today.
My Design diagrams
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Single Cycle
single cycle datapath block diagram
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Pipeline
pipeline datapath block diagram
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data cache
data cache block diagram
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data cache
data cache state diagram
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coherence controller
coherence controller state diagram